Assessment of Data Retainability of 2T DRAM for Processing-In-Memory Application

Abstract

This study examines the influence of cell capacitance on data retention characteristics in dynamic random access memory (DRAM) cells composed of two transistors, in short, 2-transistor (2T) DRAM. The 2T DRAM is gaining attention not only as a standalone memory technology but also as a critical component for processing-in-memory (PIM) applications, offering the full compatibility with standard Si processing. The 2T configuration employs separate transistors for write and read operations, enabling flexible bit-cell design and efficient parallel processing in PIM architectures. However, the small storage node (SN) capacitance, especially when the cell capacitor is truncated, poses challenges for data retention. This work presents a design methodology to enhance data retention in 2T DRAM cells by optimizing transistor dimensions and biasing schemes. Circuit simulations using the 180 nm standard process show that the proposed approach improves retention time by 35% and reduces leakage current by 22% compared to baseline designs. Furthermore, the write transistor current demonstrates a 15% improvement in stability during repeated read operations within the retention time. These results highlight the potential of the proposed design to mitigate retention-related issues and enhance computational accuracy in PIM applications.