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Analysis of Read Margin and Write Power Consumption of a 3-D vertical RRAM (VRRAM) Crossbar Array

Title
Analysis of Read Margin and Write Power Consumption of a 3-D vertical RRAM (VRRAM) Crossbar Array
Authors
Choi, SujinSun, WookyungShin, Hyungsoon
Ewha Authors
신형순선우경
SCOPUS Author ID
신형순scopus
Issue Date
2018
Journal Title
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
ISSN
2168-6734JCR Link
Citation
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY vol. 6, no. 1, pp. 1192 - 1196
Keywords
3D vertical resistive random access memory (VRRAM)bias schemecrossbar arrayread marginwrite power
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Indexed
SCIE; SCOPUS WOS scopus
Document Type
Article
Abstract
In this paper, the read margin (RM) and write power (WP) for various 3-D vertical resistive random-access memory (VRRAM) architectures and bias schemes are analyzed. The optimized bias scheme for each of the read and write operations is demonstrated using HSPICE simulation. The ground and 1/3 bias schemes are desirable for reading a row of cells and a single cell, respectively, whereas the 1/2 bias scheme is more suitable for the write operation. The RM is strongly influenced by the number of word line (WL) layers, which determines the number of half-selected cells. The WP is predominantly affected by the in-plane array size rather than the number of WL layers, as the majority of the power is consumed in the selected WL. Only slight differences between the WL plane and WL even/odd structures are observed in the RM and WP. Therefore, due to the same performance and a double cell bit, a WL even/odd structure is more promising than a WL plane structure for the VRRAM architecture.
DOI
10.1109/JEDS.2018.2873016
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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