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High cell-efficiency synchronous MRAM adopting unified bit-line cache

Title
High cell-efficiency synchronous MRAM adopting unified bit-line cache
Authors
Kim D.J.Ko J.H.Cho C.H.Park Y.I.Kang D.W.Min K.S.Kim D.M.Lee S.J.Shin H.S.
Ewha Authors
신형순
SCOPUS Author ID
신형순scopus
Issue Date
2003
Journal Title
Electronics Letters
ISSN
0013-5194JCR Link
Citation
vol. 39, no. 16, pp. 1166 - 1167
Indexed
SCI; SCIE; SCOPUS WOS scopus
Abstract
Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.
DOI
10.1049/el:20030783
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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