Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 신형순 | * |
dc.date.accessioned | 2017-01-05T02:01:17Z | - |
dc.date.available | 2017-01-05T02:01:17Z | - |
dc.date.issued | 2003 | * |
dc.identifier.issn | 0013-5194 | * |
dc.identifier.other | OAK-1587 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/233707 | - |
dc.description.abstract | Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations. | * |
dc.language | English | * |
dc.title | High cell-efficiency synchronous MRAM adopting unified bit-line cache | * |
dc.type | Article | * |
dc.relation.issue | 16 | * |
dc.relation.volume | 39 | * |
dc.relation.index | SCI | * |
dc.relation.index | SCIE | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 1166 | * |
dc.relation.lastpage | 1167 | * |
dc.relation.journaltitle | Electronics Letters | * |
dc.identifier.doi | 10.1049/el:20030783 | * |
dc.identifier.wosid | WOS:000184956300006 | * |
dc.identifier.scopusid | 2-s2.0-0042930993 | * |
dc.author.google | Kim D.J. | * |
dc.author.google | Ko J.H. | * |
dc.author.google | Cho C.H. | * |
dc.author.google | Park Y.I. | * |
dc.author.google | Kang D.W. | * |
dc.author.google | Min K.S. | * |
dc.author.google | Kim D.M. | * |
dc.author.google | Lee S.J. | * |
dc.author.google | Shin H.S. | * |
dc.contributor.scopusid | 신형순(7404012125) | * |
dc.date.modifydate | 20240322125227 | * |