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10Gbit/s 0.0065mm2 6mW analogue adaptive equaliser utilising negative capacitance

Title
10Gbit/s 0.0065mm2 6mW analogue adaptive equaliser utilising negative capacitance
Authors
Lee D.Han J.Han G.Park S.M.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2009
Journal Title
Electronics Letters
ISSN
0013-5194JCR Link
Citation
vol. 45, no. 17, pp. 863 - 865
Indexed
SCI; SCIE; SCOPUS WOS scopus
Abstract
An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10Gbit/s for 20 and 34inch FR4 traces as channels, while dissipating only 6mW from a single 1.2V supply. The chip core occupies an extremely small area of 50×130m2. To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs. © The Institution of Engineering and Technology 2009.
DOI
10.1049/el.2009.1525
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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