Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성민 | * |
dc.date.accessioned | 2016-08-29T11:08:16Z | - |
dc.date.available | 2016-08-29T11:08:16Z | - |
dc.date.issued | 2009 | * |
dc.identifier.issn | 0013-5194 | * |
dc.identifier.other | OAK-5841 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/232040 | - |
dc.description.abstract | An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10Gbit/s for 20 and 34inch FR4 traces as channels, while dissipating only 6mW from a single 1.2V supply. The chip core occupies an extremely small area of 50×130m2. To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs. © The Institution of Engineering and Technology 2009. | * |
dc.language | English | * |
dc.title | 10Gbit/s 0.0065mm2 6mW analogue adaptive equaliser utilising negative capacitance | * |
dc.type | Article | * |
dc.relation.issue | 17 | * |
dc.relation.volume | 45 | * |
dc.relation.index | SCI | * |
dc.relation.index | SCIE | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 863 | * |
dc.relation.lastpage | 865 | * |
dc.relation.journaltitle | Electronics Letters | * |
dc.identifier.doi | 10.1049/el.2009.1525 | * |
dc.identifier.wosid | WOS:000269196400002 | * |
dc.identifier.scopusid | 2-s2.0-68949105825 | * |
dc.author.google | Lee D. | * |
dc.author.google | Han J. | * |
dc.author.google | Han G. | * |
dc.author.google | Park S.M. | * |
dc.contributor.scopusid | 박성민(7501832231) | * |
dc.date.modifydate | 20240322125443 | * |