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dc.contributor.author박성민-
dc.date.accessioned2016-08-29T12:08:46Z-
dc.date.available2016-08-29T12:08:46Z-
dc.date.issued2015-
dc.identifier.isbn9781467393089-
dc.identifier.otherOAK-18541-
dc.identifier.urihttp://dspace.ewha.ac.kr/handle/2015.oak/231528-
dc.description.abstractThis paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2. © 2015 IEEE.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.subjectCMOS-
dc.subjectfrequency synthesizer-
dc.subjectPLL-
dc.subjectring VCO-
dc.subjecttuning range-
dc.titleA 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS-
dc.typeConference Paper-
dc.relation.indexSCOPUS-
dc.relation.startpage235-
dc.relation.lastpage236-
dc.relation.journaltitleISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)-
dc.identifier.doi10.1109/ISOCC.2015.7401734-
dc.identifier.scopusid2-s2.0-84963865336-
dc.author.googleLee K.-
dc.author.googleHong C.-
dc.author.googleYing H.-
dc.author.googleKim D.-
dc.author.googleKim S.H.-
dc.author.googlePark S.M.-
dc.contributor.scopusid박성민(7501832231)-
dc.date.modifydate20170922131745-
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엘텍공과대학 > 전자공학과 > Journal papers
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