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A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS
- Title
- A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS
- Authors
- Lee K.; Hong C.; Ying H.; Kim D.; Kim S.H.; Park S.M.
- Ewha Authors
- 박성민
- SCOPUS Author ID
- 박성민
- Issue Date
- 2015
- Journal Title
- ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
- Citation
- ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), pp. 235 - 236
- Keywords
- CMOS; frequency synthesizer; PLL; ring VCO; tuning range
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Indexed
- SCOPUS
- Document Type
- Conference Paper
- Abstract
- This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2. © 2015 IEEE.
- DOI
- 10.1109/ISOCC.2015.7401734
- ISBN
- 9781467393089
- Appears in Collections:
- 공과대학 > 전자전기공학전공 > Journal papers
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