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A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications

Title
A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications
Authors
Yoo K.Han G.Park S.M.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2006
Journal Title
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Indexed
SCOPUS scopus
Abstract
In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply. ©2006 IEEE.
DOI
10.1109/ICECS.2006.379844
ISBN
1424403952; 9781424403950
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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