DSpace at EWHA: A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications

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DC Field	Value	Language
dc.contributor.author	박성민	*
dc.date.accessioned	2016-08-28T11:08:47Z	-
dc.date.available	2016-08-28T11:08:47Z	-
dc.date.issued	2006	*
dc.identifier.isbn	1424403952	*
dc.identifier.isbn	9781424403950	*
dc.identifier.other	OAK-13076	*
dc.identifier.uri	https://dspace.ewha.ac.kr/handle/2015.oak/229113	-
dc.description.abstract	In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply. ©2006 IEEE.	*
dc.description.sponsorship	IEEE;IEEE Section France	*
dc.language	English	*
dc.title	A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications	*
dc.type	Conference Paper	*
dc.relation.index	SCOPUS	*
dc.relation.startpage	537	*
dc.relation.lastpage	540	*
dc.relation.journaltitle	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems	*
dc.identifier.doi	10.1109/ICECS.2006.379844	*
dc.identifier.scopusid	2-s2.0-47349119889	*
dc.author.google	Yoo K.	*
dc.author.google	Han G.	*
dc.author.google	Park S.M.	*
dc.contributor.scopusid	박성민(7501832231)	*
dc.date.modifydate	20240322125443	*