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An efficient built-in self-test algorithm for neighborhood pattern- and bit-line-sensitive faults in high-density memories

Title
An efficient built-in self-test algorithm for neighborhood pattern- and bit-line-sensitive faults in high-density memories
Authors
Kang D.-C.Park S.M.Cho S.-B.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2004
Journal Title
ETRI Journal
ISSN
1225-6463JCR Link
Citation
vol. 26, no. 6, pp. 520 - 534
Indexed
SCI; SCIE; SCOPUS; KCI WOS scopus
Abstract
As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.
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엘텍공과대학 > 전자공학과 > Journal papers
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