Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers vol. 43, no. 4 B, pp. 2226 - 2229
SCI; SCIE; SCOPUS
A novel sensing scheme for a magneto-resistive random access memory (MRAM) with a twin cell structure is presented. New sensing circuit has very simple structure while providing stable operation. Voltage-controlled transistor switch limits the voltage across the magnetic tunnel junction (MTJ) under 400 mV while reading. The circuit layout is small enough to fit into 4-cell pitches that high speed synchronous operation is made possible in MRAMs as in DRAMs or SRAMs. We have fully integrated a 256 bit synchronous MRAM operating at 100 MHz with 0.35 um complementary metal oxide semiconductor (CMOS) technology.