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dc.contributor.author신형순-
dc.contributor.author이승준-
dc.date.accessioned2017-08-28T10:37:11Z-
dc.date.available2017-08-28T10:37:11Z-
dc.date.issued2004-
dc.identifier.issn0021-4922-
dc.identifier.otherOAK-2174-
dc.identifier.urihttp://dspace.ewha.ac.kr/handle/2015.oak/219429-
dc.description.abstractA novel sensing scheme for a magneto-resistive random access memory (MRAM) with a twin cell structure is presented. New sensing circuit has very simple structure while providing stable operation. Voltage-controlled transistor switch limits the voltage across the magnetic tunnel junction (MTJ) under 400 mV while reading. The circuit layout is small enough to fit into 4-cell pitches that high speed synchronous operation is made possible in MRAMs as in DRAMs or SRAMs. We have fully integrated a 256 bit synchronous MRAM operating at 100 MHz with 0.35 um complementary metal oxide semiconductor (CMOS) technology.-
dc.languageEnglish-
dc.titleA novel sensing circuit for high speed synchronous magneto-resistive RAM-
dc.typeConference Paper-
dc.relation.issue4 B-
dc.relation.volume43-
dc.relation.indexSCI-
dc.relation.indexSCIE-
dc.relation.indexSCOPUS-
dc.relation.startpage2226-
dc.relation.lastpage2229-
dc.relation.journaltitleJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers-
dc.identifier.wosidWOS:000221510800128-
dc.identifier.scopusid2-s2.0-3142603167-
dc.author.googleKim H.-
dc.author.googleLee S.-
dc.author.googleShin H.-
dc.author.googleKim D.-
dc.contributor.scopusid신형순(7404012125)-
dc.contributor.scopusid이승준(36064894500)-
dc.date.modifydate20170922131752-
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엘텍공과대학 > 전자공학과 > Journal papers
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