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Clock distribution scheme for high-speed DRAM

Title
Clock distribution scheme for high-speed DRAM
Authors
Kook, JWee, JKMoon, GLee, S
Ewha Authors
이승준
SCOPUS Author ID
이승준scopus
Issue Date
2002
Journal Title
ELECTRONICS LETTERS
ISSN
0013-5194JCR Link
Citation
vol. 38, no. 13, pp. 626 - 627
Publisher
IEE-INST ELEC ENG
Indexed
SCI; SCIE; SCOPUS WOS
Abstract
A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results shock that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage and temperature variations.
DOI
10.1049/el:20020446
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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