Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 이승준 | * |
dc.date.accessioned | 2016-08-27T02:08:42Z | - |
dc.date.available | 2016-08-27T02:08:42Z | - |
dc.date.issued | 2002 | * |
dc.identifier.issn | 0013-5194 | * |
dc.identifier.other | OAK-1101 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/215517 | - |
dc.description.abstract | A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results shock that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage and temperature variations. | * |
dc.language | English | * |
dc.publisher | IEE-INST ELEC ENG | * |
dc.title | Clock distribution scheme for high-speed DRAM | * |
dc.type | Article | * |
dc.relation.issue | 13 | * |
dc.relation.volume | 38 | * |
dc.relation.index | SCI | * |
dc.relation.index | SCIE | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 626 | * |
dc.relation.lastpage | 627 | * |
dc.relation.journaltitle | ELECTRONICS LETTERS | * |
dc.identifier.doi | 10.1049/el:20020446 | * |
dc.identifier.wosid | WOS:000176632500009 | * |
dc.author.google | Kook, J | * |
dc.author.google | Wee, JK | * |
dc.author.google | Moon, G | * |
dc.author.google | Lee, S | * |
dc.contributor.scopusid | 이승준(36064894500;57207064952) | * |
dc.date.modifydate | 20240322125312 | * |