CMOS compatible probabilistic computing hardware with cointegrated reconfigurable p-bits and synapse arrays

Abstract

Probabilistic computing (p-computing) has emerged as a promising approach to solve combinatorial optimization problems (COPs) at room temperature, offering a practical alternative to quantum computing. Scalable p-computing hardware requires integration of probabilistic bits (p-bits) and synapses, two components with inherently contrasting device requirements. Here, we present a charge-trap field-effect transistor (CT-FET) with a silicon-oxide-nitride-silicon gate stack that functions reconfigurably as both a p-bit and a synapse, derived from a commercialized flash memory structure. Gate voltage control of trap energy enables stochastic shallow trap operation for p-bits and stable deep trap operation for synapses. P-bits and synapse array are cointegrated on a single wafer using standard CMOS processes, enabling scalable p-computing hardware. Experimental validation shows successful solution of a 4-node weighted max-cut problem including negative weights, while simulations confirm efficient solution of a 20-node weighted max-cut problem including negative weights via chaotic simulated annealing. These results demonstrate a CMOS compatible pathway toward practical and scalable probabilistic processors. © The Author(s) 2026.