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An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network

Title
An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network
Authors
Shah, Arati KumariUdaya Mohanan, KannanPark, JisunShin, HyungsoonCho, Eou-SikCho, Seongjae
Ewha Authors
신형순박지선조성재
SCOPUS Author ID
신형순scopus; 박지선scopus; 조성재scopus
Issue Date
2023
Journal Title
IET CIRCUITS DEVICES & SYSTEMS
ISSN
1751-858XJCR Link

1751-8598JCR Link
Citation
IET CIRCUITS DEVICES & SYSTEMS vol. 2023
Publisher
WILEY-HINDAWI
Indexed
SCIE; SCOPUS WOS
Document Type
Article
Abstract
Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-mu m Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 mu W per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.
DOI
10.1049/2023/1052063
Appears in Collections:
공과대학 > 전자전기공학전공 > Journal papers
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