Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김지훈 | * |
dc.date.accessioned | 2023-01-18T16:32:54Z | - |
dc.date.available | 2023-01-18T16:32:54Z | - |
dc.date.issued | 2022 | * |
dc.identifier.issn | 1549-8328 | * |
dc.identifier.other | OAK-32850 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/263856 | - |
dc.description.abstract | Recently, there is increasing demand for energy-efficient signal processing in wearable visual-stimuli-based brain-computer interface (V-BCI) devices. For the better accuracy and the reduced latency of the V-BCI system, the target identification (TI) algorithm that analyzes brain signals is being advanced, and the importance of an energy-efficient accelerating chip that processes various linear algebra operations constituting the TI algorithms is growing. In this paper, we propose a domain-specific reconfigurable array processor (RAP) with a dynamically reconfigurable and scalable array including 5-heterogeneous processing elements (PEs) for the energy-efficient acceleration of basic linear algebra subprograms (BLAS) and matrix decompositions. The system-on-chip (SoC), including the proposed RAP, was fabricated in 130-nm CMOS technology with an area of 16.87-mm2 and measured at 1.0 V 90 MHz. The RAP achieved an information transfer rate (ITR) of 139.9-bits/min and a TI accuracy of 95.4% on a fabricated chip through an optimized TI algorithm and scalable array processing. In addition, the RAP has $16.8\times $ higher TI energy efficiency than prior work and achieved an energy efficiency of 2144.2-bits/min/mW for information transfer processing rate with the proposed TI algorithm. The RAP supports a greater variety of linear algebra operations and data sizes with hardware reconfiguration than the prior accelerators. © 2004-2012 IEEE. | * |
dc.language | English | * |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | * |
dc.subject | Brain-computer interface (BCI) | * |
dc.subject | domain-specific architecture | * |
dc.subject | heterogeneous PE | * |
dc.subject | linear algebra accelerator | * |
dc.subject | reconfigurable array processor | * |
dc.title | An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs | * |
dc.type | Article | * |
dc.relation.issue | 12 | * |
dc.relation.volume | 69 | * |
dc.relation.index | SCIE | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 4872 | * |
dc.relation.lastpage | 4885 | * |
dc.relation.journaltitle | IEEE Transactions on Circuits and Systems I: Regular Papers | * |
dc.identifier.doi | 10.1109/TCSI.2022.3197186 | * |
dc.identifier.scopusid | 2-s2.0-85136846385 | * |
dc.author.google | Byun W. | * |
dc.author.google | Je M. | * |
dc.author.google | Kim J.-H. | * |
dc.contributor.scopusid | 김지훈(57214339649) | * |
dc.date.modifydate | 20240322130321 | * |