Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 이상욱 | * |
dc.date.accessioned | 2021-06-07T16:31:36Z | - |
dc.date.available | 2021-06-07T16:31:36Z | - |
dc.date.issued | 2021 | * |
dc.identifier.issn | 1616-301X | * |
dc.identifier.other | OAK-29339 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/257651 | - |
dc.description.abstract | In this study, high-performance few-layered ReS2 field-effect transistors (FETs), fabricated with hexagonal boron nitride (h-BN) as top/bottom dual gate dielectrics, are presented. The performance of h-BN dual gated ReS2 FET having a trade-off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h-BN dielectric has almost no defects and provides a physical distance between the traps in the SiO2 and the carriers in the ReS2 channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h-BN dual-gated ReS2 with a high mobility of 46.1 cm2 V−1 s−1, a high current on/off ratio of ≈106, a subthreshold swing of 2.7 V dec−1, and a low effective interface trap density (Nt,eff) of 7.85 × 1010 cm−2 eV−1 at a small operating voltage (<3 V). These phenomena are demonstrated through not only a fundamental current–voltage analysis, but also technology computer aided design simulations, time-dependent current, and low-frequency noise analysis. In addition, a simple method is introduced to extract the interlayer resistance of ReS2 channel through Y-function method as a function of constant top gate bias. © 2021 Wiley-VCH GmbH | * |
dc.language | English | * |
dc.publisher | John Wiley and Sons Inc | * |
dc.subject | 2D materials | * |
dc.subject | defects | * |
dc.subject | dual-gate ReS2 | * |
dc.subject | field-effect transistors | * |
dc.subject | hexagonal boron nitride | * |
dc.title | Modeling and Understanding the Compact Performance of h-BN Dual-Gated ReS2 Transistor | * |
dc.type | Article | * |
dc.relation.issue | 23 | * |
dc.relation.volume | 31 | * |
dc.relation.index | SCIE | * |
dc.relation.index | SCOPUS | * |
dc.relation.journaltitle | Advanced Functional Materials | * |
dc.identifier.doi | 10.1002/adfm.202100625 | * |
dc.identifier.wosid | WOS:000635455800001 | * |
dc.identifier.scopusid | 2-s2.0-85103975333 | * |
dc.author.google | Lee K. | * |
dc.author.google | Choi J. | * |
dc.author.google | Kaczer B. | * |
dc.author.google | Grill A. | * |
dc.author.google | Lee J.W. | * |
dc.author.google | Van Beek S. | * |
dc.author.google | Bury E. | * |
dc.author.google | Diaz-Fortuny J. | * |
dc.author.google | Chasin A. | * |
dc.author.google | Lee J. | * |
dc.author.google | Chun J. | * |
dc.author.google | Shin D.H. | * |
dc.author.google | Na J. | * |
dc.author.google | Cho H. | * |
dc.author.google | Lee S.W. | * |
dc.author.google | Kim G.-T. | * |
dc.contributor.scopusid | 이상욱(57254781200) | * |
dc.date.modifydate | 20240222165214 | * |