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Memory-Reduced Non-Binary LDPC Decoding With Accumulative Bubble Check
- Title
- Memory-Reduced Non-Binary LDPC Decoding With Accumulative Bubble Check
- Authors
- Choi, Injun; Kim, Ji-Hoon
- Ewha Authors
- 김지훈
- SCOPUS Author ID
- 김지훈
- Issue Date
- 2018
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- ISSN
- 1549-7747
1558-3791
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS vol. 65, no. 11, pp. 1619 - 1623
- Keywords
- Accumulative bubble check; memory-reduction; non-binary low-density parity check codes; non-uniform memory
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Indexed
- SCIE; SCOPUS
- Document Type
- Article
- Abstract
- Non-binary (NB) low-density parity check (LDPC) codes offer stronger error correcting capability than binary LDPC codes. However, the improvement is accompanied by a considerable increase in the decoding complexity and a huge memory requirement, especially in the check node (CN). To overcome these limitations, we propose a memory-reduced NB-LDPC decoding method with an accumulative bubble check (a-bubble check) algorithm. The proposed a-bubble check reduces the memory requirements of the CNs by using the differences between the log-likelihood ratio entries. In addition, we propose a non-uniform memory structure to further decrease the memory capacity of the CN processor. For the GF(64)(160, 80) NB-LDPC code, the proposed memory-reduced NB-LDPC decoding architecture achieves a memory requirement reduction of 32.4% for the CNs and 16.2% for the entire decoder without degrading the error correction capability.
- DOI
- 10.1109/TCSII.2017.2761790
- Appears in Collections:
- 공과대학 > 전자전기공학전공 > Journal papers
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