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dc.contributor.author지창현-
dc.date.accessioned2016-08-28T10:08:41Z-
dc.date.available2016-08-28T10:08:41Z-
dc.date.issued2012-
dc.identifier.issn0960-1317-
dc.identifier.otherOAK-9158-
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/222965-
dc.description.abstractA double-sided wet etch process has been proposed to fabricate vertical structures in 〈100〉 oriented silicon substrate. Both sides of a {100} silicon wafer have been patterned identically along the 〈110〉 direction, and etched using potassium hydroxide (KOH) solution. By precisly controlling the etch time, using etch-timer structure and additive control, structures with smooth and vertical {110} sidewalls have been fabricated at the edges of a rectangular opening without undercut. Rectangular through-holes, bridges and cantilevers have been constructed using the proposed process. The measured average surface roughness of the vertical sidewall was 481nm, which has been further reduced to 217nm and 218nm by postetching using a KOH-IPA and TMAH-Triton mixture, respectively. Slanted {411} planes exposed at the concave corners during the vertical etch process have been successfully removed or diminished by the postetching process. A bridge structure with a high aspect ratio of 39:1 has been fabricated, and cantilevers without undercutting were successfully constructed by applying the compensation technique. The proposed process can potentially be utilized in place of the deep reactive ion etching process for the fabrication of structures having vertical through-holes, such as through-silicon vias, high aspect ratio springs and filters for microfluidic applications. © 2012 IOP Publishing Ltd.-
dc.languageEnglish-
dc.titleFabrication of a vertical sidewall using double-sided anisotropic etching of 〈100〉 oriented silicon-
dc.typeArticle-
dc.relation.issue9-
dc.relation.volume22-
dc.relation.indexSCIE-
dc.relation.indexSCOPUS-
dc.relation.journaltitleJournal of Micromechanics and Microengineering-
dc.identifier.doi10.1088/0960-1317/22/9/095014-
dc.identifier.wosidWOS:000308210600024-
dc.identifier.scopusid2-s2.0-84866321456-
dc.author.googleKim H.-S.-
dc.author.googleKim J.-M.-
dc.author.googleBang Y.-S.-
dc.author.googleSong E.-S.-
dc.author.googleJi C.-H.-
dc.author.googleKim Y.-K.-
dc.contributor.scopusid지창현(7202015390)-
dc.date.modifydate20180104081001-
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엘텍공과대학 > 전자공학과 > Journal papers
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