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dc.contributor.author이승준-
dc.date.accessioned2016-08-27T02:08:42Z-
dc.date.available2016-08-27T02:08:42Z-
dc.date.issued2002-
dc.identifier.issn0013-5194-
dc.identifier.otherOAK-1101-
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/215517-
dc.description.abstractA novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results shock that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage and temperature variations.-
dc.languageEnglish-
dc.publisherIEE-INST ELEC ENG-
dc.titleClock distribution scheme for high-speed DRAM-
dc.typeArticle-
dc.relation.issue13-
dc.relation.volume38-
dc.relation.indexSCI-
dc.relation.indexSCIE-
dc.relation.indexSCOPUS-
dc.relation.startpage626-
dc.relation.lastpage627-
dc.relation.journaltitleELECTRONICS LETTERS-
dc.identifier.doi10.1049/el:20020446-
dc.identifier.wosidWOS:000176632500009-
dc.author.googleKook, J-
dc.author.googleWee, JK-
dc.author.googleMoon, G-
dc.author.googleLee, S-
dc.contributor.scopusid이승준(36064894500;57207064952)-
dc.date.modifydate20211210154130-
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엘텍공과대학 > 전자공학과 > Journal papers
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