View : 290 Download: 0
A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
- A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
- Kim, Sang Gyun; Hong, Chaerin; Eo, Yun Seong; Kim, Jihoon; Park, Sung Min
- Ewha Authors
- 박성민; 김지훈
- SCOPUS Author ID
- Issue Date
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. 54, no. 5, pp. 1468 - 1474
- Asymmetric transformers; CMOS; mirrored cascode (MC); single to differential; transimpedance amplifier (TIA)
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- SCIE; SCOPUS
- Document Type
- This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i. e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Omega transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA/root Hz average noise current spectral density, +/- 10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215-1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.
- Appears in Collections:
- 엘텍공과대학 > 전자공학과 > Journal papers
- Files in This Item:
There are no files associated with this item.
- RIS (EndNote)
- XLS (Excel)
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.