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A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

Title
A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
Authors
Kim, Sang GyunHong, ChaerinEo, Yun SeongKim, JihoonPark, Sung Min
Ewha Authors
박성민김지훈
SCOPUS Author ID
박성민scopus
Issue Date
2019
Journal Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN
0018-9200JCR Link

1558-173XJCR Link
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. 54, no. 5, pp. 1468 - 1474
Keywords
Asymmetric transformersCMOSmirrored cascode (MC)single to differentialtransimpedance amplifier (TIA)
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Indexed
SCIE; SCOPUS WOS scopus
Document Type
Article
Abstract
This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i. e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Omega transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA/root Hz average noise current spectral density, +/- 10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215-1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.
DOI
10.1109/JSSC.2018.2886323
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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