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dc.contributor.author임혜숙*
dc.date.accessioned2019-06-04T16:30:04Z-
dc.date.available2019-06-04T16:30:04Z-
dc.date.issued2019*
dc.identifier.isbn9788995004449*
dc.identifier.otherOAK-24859*
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/249898-
dc.description.abstractThis paper presents an IP address lookup architecture constructed with a vectored-Bloom filter (VBF) to perform the longest prefix matching. The VBF is an efficient structure to obtain the output port of each input IP address without accessing an off-chip memory. This paper demonstrates that the proposed IP address lookup architecture parallelly implemented on an FPGA can achieve the high performance in terms of the search speed and the throughput. © 2019 Institute of Electronics and Information Engineers (IEIE).*
dc.languageEnglish*
dc.publisherInstitute of Electrical and Electronics Engineers Inc.*
dc.subjectFPGA*
dc.subjectHardware accelerator*
dc.subjectIP address lookup*
dc.subjectVectored-Bloom filter*
dc.titleVectored-bloom filter implemented on FPGA for IP address lookup*
dc.typeConference Paper*
dc.relation.indexSCOPUS*
dc.relation.journaltitleICEIC 2019 - International Conference on Electronics, Information, and Communication*
dc.identifier.doi10.23919/ELINFOCOM.2019.8706399*
dc.identifier.scopusid2-s2.0-85065867164*
dc.author.googleByun H.*
dc.author.googleLi Q.*
dc.author.googleLim H.*
dc.contributor.scopusid임혜숙(7403095209)*
dc.date.modifydate20240419140241*
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공과대학 > 전자전기공학전공 > Journal papers
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