Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성민 | * |
dc.date.accessioned | 2018-06-06T08:13:08Z | - |
dc.date.available | 2018-06-06T08:13:08Z | - |
dc.date.issued | 2007 | * |
dc.identifier.issn | 0271-4310 | * |
dc.identifier.other | OAK-17829 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/244682 | - |
dc.description.abstract | In this paper, a four-channel 12.5-Gb/s differential transimpedance amplifier (TIA) array is realized in a 0.18-μm standard CMOS technology for the applications of digital visual interface (DVI) and high-definition multimedia interface (HDMI) cables. By exploiting the common-gate configuration as input stage, the TIA relaxes the design tradeoffs between the bandwidth and the large photodiode capacitance. Post-layout simulations demonstrate that a single channel TIA achieves 64-dBΩ transimpedance gain, 3.125-Gb/s operations with 2.1-GHz bandwidth for 2-pF input parasitic capacitance including photodiode capacitance and ESD protection pad capacitance, and 1.52-μA average input noise current that corresponds to -18dBm sensitivity for 10 -12 BER The 4-channel TIA array consumes 200-mW from a single 1.8-V supply. © 2007 IEEE. | * |
dc.language | English | * |
dc.title | A 4-channel 12.5Gb/s common-gate transimpedance amplifier array for DVI/HDMI applications | * |
dc.type | Conference Paper | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 2192 | * |
dc.relation.lastpage | 2195 | * |
dc.relation.journaltitle | Proceedings - IEEE International Symposium on Circuits and Systems | * |
dc.identifier.scopusid | 2-s2.0-34548837513 | * |
dc.author.google | Park K. | * |
dc.author.google | Oh W.S. | * |
dc.author.google | Choi B.-Y. | * |
dc.author.google | Han J.-W. | * |
dc.author.google | Park S.M. | * |
dc.contributor.scopusid | 박성민(7501832231) | * |
dc.date.modifydate | 20240322125443 | * |