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dc.contributor.author박성민-
dc.date.accessioned2018-06-06T08:13:08Z-
dc.date.available2018-06-06T08:13:08Z-
dc.date.issued2007-
dc.identifier.issn0271-4310-
dc.identifier.otherOAK-17829-
dc.identifier.urihttp://dspace.ewha.ac.kr/handle/2015.oak/244682-
dc.description.abstractIn this paper, a four-channel 12.5-Gb/s differential transimpedance amplifier (TIA) array is realized in a 0.18-μm standard CMOS technology for the applications of digital visual interface (DVI) and high-definition multimedia interface (HDMI) cables. By exploiting the common-gate configuration as input stage, the TIA relaxes the design tradeoffs between the bandwidth and the large photodiode capacitance. Post-layout simulations demonstrate that a single channel TIA achieves 64-dBΩ transimpedance gain, 3.125-Gb/s operations with 2.1-GHz bandwidth for 2-pF input parasitic capacitance including photodiode capacitance and ESD protection pad capacitance, and 1.52-μA average input noise current that corresponds to -18dBm sensitivity for 10 -12 BER The 4-channel TIA array consumes 200-mW from a single 1.8-V supply. © 2007 IEEE.-
dc.languageEnglish-
dc.titleA 4-channel 12.5Gb/s common-gate transimpedance amplifier array for DVI/HDMI applications-
dc.typeConference Paper-
dc.relation.indexSCOPUS-
dc.relation.startpage2192-
dc.relation.lastpage2195-
dc.relation.journaltitleProceedings - IEEE International Symposium on Circuits and Systems-
dc.identifier.scopusid2-s2.0-34548837513-
dc.author.googlePark K.-
dc.author.googleOh W.S.-
dc.author.googleChoi B.-Y.-
dc.author.googleHan J.-W.-
dc.author.googlePark S.M.-
dc.contributor.scopusid박성민(7501832231)-
dc.date.modifydate20180605150031-
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엘텍공과대학 > 전자공학과 > Journal papers
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