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dc.contributor.author이상욱*
dc.date.accessioned2017-05-09T01:05:40Z-
dc.date.available2017-05-09T01:05:40Z-
dc.date.issued2017*
dc.identifier.issn0957-4484*
dc.identifier.issn1361-6528*
dc.identifier.otherOAK-20532*
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/235070-
dc.description.abstractThe modulation of charge carrier concentration allows us to tune the Fermi level (EF) of graphene thanks to the low electronic density of states near the EF. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed EF-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p-and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The EF modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.*
dc.languageEnglish*
dc.publisherIOP PUBLISHING LTD*
dc.subjectgraphene doping*
dc.subjectMoSe2*
dc.subjectp-n junction*
dc.titleA reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications*
dc.typeArticle*
dc.relation.issue17*
dc.relation.volume28*
dc.relation.indexSCIE*
dc.relation.indexSCOPUS*
dc.relation.journaltitleNANOTECHNOLOGY*
dc.identifier.doi10.1088/1361-6528/aa6537*
dc.identifier.wosidWOS:000398393700004*
dc.identifier.scopusid2-s2.0-85017437411*
dc.author.googleKim, Seonyeong*
dc.author.googleShin, Somyeong*
dc.author.googleKim, Taekwang*
dc.author.googleDu, Hyewon*
dc.author.googleSong, Minho*
dc.author.googleKim, Ki Soo*
dc.author.googleCho, Seungmin*
dc.author.googleLee, Sang Wook*
dc.author.googleSeo, Sunae*
dc.contributor.scopusid이상욱(57254781200)*
dc.date.modifydate20240222165214*
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자연과학대학 > 물리학전공 > Journal papers
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