The dynamic characteristics of a spin transfer torque magnetoresistive random access memory crossbar array during write operations were investigated. A spin transfer torque magnetic tunnel junction was combined with a two-terminal selector device instead of a three-terminal CMOS transistor in the crossbar array architecture. The characteristics of the crossbar array architecture were investigated under different bias schemes and transient simulations of write operations were performed under various operating conditions. The variance of the switching time and problematic behaviors was investigated. The floating bias scheme was compared with the 1/2 bias scheme, and simulation results revealed that write errors may be induced in the floating bias scheme by abnormal glitches occurring when the parasitic capacitance becomes large.