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dc.contributor.author신형순*
dc.date.accessioned2016-08-29T12:08:19Z-
dc.date.available2016-08-29T12:08:19Z-
dc.date.issued2015*
dc.identifier.isbn9781479942039*
dc.identifier.otherOAK-15273*
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/230694-
dc.description.abstractPower consumption of large-scale crossbar array architecture is investigated by the comprehensive crossbar array matrix model. The power dissipation is examined as functions of array size, leakage current of selector, and various bias schemes. The power consumption increases as the array size and the leakage current of selector increases. In addition, 1/3 bias scheme shows power consumption about 1∼2 orders of magnitude larger than other bias schemes. This phenomenon is induced from the unselected cells which is delivered with voltage about V<inf>dd</inf>/3, whereas the voltage of unselected cells are almost 0 V for 1/2 bias and floating bias schemes. © 2014 IEEE.*
dc.description.sponsorshipCOSAR;Jeju Tourism Organization;Korea Tourism Organization;Yonsei Institute of Green Technology (YIGT)*
dc.languageEnglish*
dc.publisherInstitute of Electrical and Electronics Engineers Inc.*
dc.subjectcrossbar array*
dc.subjectpower dissipation*
dc.subjectReRAM*
dc.titleInvestigation of power dissipation for ReRAM in crossbar array architecture*
dc.typeConference Paper*
dc.relation.indexSCOPUS*
dc.relation.journaltitle2014 14th Annual Non-Volatile Memory Technology Symposium, NVMTS 2014*
dc.identifier.doi10.1109/NVMTS.2014.7060847*
dc.identifier.scopusid2-s2.0-84936796819*
dc.author.googleSun W.*
dc.author.googleLim H.*
dc.author.googleShin H.*
dc.author.googleLee W.*
dc.contributor.scopusid신형순(7404012125)*
dc.date.modifydate20240322125227*
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공과대학 > 전자전기공학전공 > Journal papers
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