Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성민 | * |
dc.date.accessioned | 2016-08-28T11:08:50Z | - |
dc.date.available | 2016-08-28T11:08:50Z | - |
dc.date.issued | 2007 | * |
dc.identifier.isbn | 1424413605 | * |
dc.identifier.isbn | 9781424413607 | * |
dc.identifier.other | OAK-13115 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/229149 | - |
dc.description.abstract | This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18μm CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5Gb/s, equipped with the APC (5-15mA) and AMC (4-20mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87dBΩ transimpedance gain, 1.4GHz bandwidth for 2pF input parasitic capacitance, -18dBm sensitivity for 10-12 BER, and less than -20dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500mW. ©2007 IEEE. | * |
dc.language | English | * |
dc.title | A 2.5Gb/s ESD-protected dual-channel optical transceiver array | * |
dc.type | Conference Paper | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 156 | * |
dc.relation.lastpage | 159 | * |
dc.relation.journaltitle | 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC | * |
dc.identifier.doi | 10.1109/ASSCC.2007.4425754 | * |
dc.identifier.scopusid | 2-s2.0-51349084673 | * |
dc.author.google | Han J. | * |
dc.author.google | Choi B. | * |
dc.author.google | Park K. | * |
dc.author.google | Oh W.S. | * |
dc.author.google | Park S.M. | * |
dc.contributor.scopusid | 박성민(7501832231) | * |
dc.date.modifydate | 20240322125443 | * |