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dc.contributor.author박성민*
dc.date.accessioned2016-08-28T11:08:50Z-
dc.date.available2016-08-28T11:08:50Z-
dc.date.issued2007*
dc.identifier.isbn1424413605*
dc.identifier.isbn9781424413607*
dc.identifier.otherOAK-13115*
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/229149-
dc.description.abstractThis paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18μm CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5Gb/s, equipped with the APC (5-15mA) and AMC (4-20mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87dBΩ transimpedance gain, 1.4GHz bandwidth for 2pF input parasitic capacitance, -18dBm sensitivity for 10-12 BER, and less than -20dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500mW. ©2007 IEEE.*
dc.languageEnglish*
dc.titleA 2.5Gb/s ESD-protected dual-channel optical transceiver array*
dc.typeConference Paper*
dc.relation.indexSCOPUS*
dc.relation.startpage156*
dc.relation.lastpage159*
dc.relation.journaltitle2007 IEEE Asian Solid-State Circuits Conference, A-SSCC*
dc.identifier.doi10.1109/ASSCC.2007.4425754*
dc.identifier.scopusid2-s2.0-51349084673*
dc.author.googleHan J.*
dc.author.googleChoi B.*
dc.author.googlePark K.*
dc.author.googleOh W.S.*
dc.author.googlePark S.M.*
dc.contributor.scopusid박성민(7501832231)*
dc.date.modifydate20240322125443*
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공과대학 > 전자전기공학전공 > Journal papers
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