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An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer

Title
An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer
Authors
Lee D.Han J.Han G.Park S.M.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2010
Journal Title
IEEE Journal of Solid-State Circuits
ISSN
0018-9200JCR Link
Citation
vol. 45, no. 12, pp. 2861 - 2873
Indexed
SCI; SCIE; SCOPUS WOS scopus
Abstract
An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13- μm CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB Ω transimpedance gain, 5.9-GHz bandwidth, - 3.2-dBm optical sensitivity for 10 -12 BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm 2. © 2006 IEEE.
DOI
10.1109/JSSC.2010.2077050
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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