SpDRAM: Efficient In-DRAM Acceleration of Sparse Matrix-Vector Multiplication

Abstract

We introduce novel sparsity-aware in-DRAM matrix mapping techniques and a correspondingDRAM-based acceleration framework, termedSpDRAM, which utilizes a triple row activation schemeto efficiently handle sparse matrix-vector multiplication (SpMV). We found that reducing operationsby sparsity relies heavily on how matrices are mapped into DRAM banks, which operate row byrow. These banks operate row by row. From this insight, we developed two distinct matrix mappingtechniques aimed at maximizing the reduction of row operations with minimal design overhead: Output-aware Matrix Permutation (OMP) and Zero-aware Matrix Column Sorting (ZMCS). Additionally,we propose a Multiplication Deferring (MD) scheme that leverages the prevalent bit-level sparsity inmatrix values to decrease the effective bit-width required for in-bank multiplication operations. Evaluationresults demonstrate that the combination of our in-DRAM acceleration methods outperforms the latestDRAM-based PIM accelerator for SpMV, achieving a performance increase of up to 7.54xand a 22.4ximprovement in energy efficiency in a wide range of SpMV tasks