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Combining memory allocation and processor volatage scaling for energy-efficient IoT task scheduling
- Title
- Combining memory allocation and processor volatage scaling for energy-efficient IoT task scheduling
- Authors
- Nam S.A.; Cho K.; Bahn H.
- Ewha Authors
- 반효경; 조경운
- SCOPUS Author ID
- 반효경; 조경운
- Issue Date
- 2017
- Journal Title
- Proceedings - 16th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2017
- Citation
- Proceedings - 16th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2017, pp. 441 - 446
- Keywords
- Dynamic voltage scaling; Hybrid memory; Internet-of-things (IoT); Non-volatile memory; Real-time task scheduling
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Indexed
- SCOPUS
- Document Type
- Conference Paper
- Abstract
- As IoT (Internet-of-things) technologies grow rapidly for emerging applications such as smart living and health care, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, of which power-savings have been widely studied in terms of processor's dynamic voltage/frequency scaling. However, recent research has shown that memory subsystems are getting reached to a significant portion of power consumption in such systems. In this paper, we show that power consumption of real-time systems can be further reduced by combining voltage/frequency scaling with task allocation in hybrid memory. If a task set is schedulable in a low voltage mode of a processor, we can expect that the task set will still be schedulable even with slow memory. By considering this, we adopt non-volatile memory technologies that consume less power than DRAM but provide relatively slow access latency. Our aim is to allocate tasks in non-volatile memory if it does not violate the deadline constraint of real-time tasks, thereby reducing the power consumption of the system further. To do so, we incorporate the memory allocation problem into the problem model of processor's voltage scaling, and evaluate the effectiveness of the combined approach. © 2017 IEEE.
- DOI
- 10.1109/ICIS.2017.7960033
- ISBN
- 9781509055074
- Appears in Collections:
- 인공지능대학 > 컴퓨터공학과 > Journal papers
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