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dc.contributor.author이병욱-
dc.date.accessioned2016-08-28T11:08:35Z-
dc.date.available2016-08-28T11:08:35Z-
dc.date.issued1998-
dc.identifier.issn1053-587X-
dc.identifier.otherOAK-12524-
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/228653-
dc.description.abstractThis paper proposes hardware architectures of adaptive equalizers applicable to both the quadrature amplitude modulation (QAM) and vestigial sideband modulation (VSB) systems. First, adaptive equalization algorithms for QAM and VSB systems are presented by modifying the constant modulus algorithm (CMA) and least mean squares (LMS) algorithm, and their hardware mapping procedure is described. The proposed digitization methods requiring a low hardware cost show performance comparable with that of the algorithm employing floating-point operations. To reduce the hardware cost of the high-definition television (HDTV) equalizers, we propose a pipelined architecture that processes some parallel parts sequentially. The synthesis results by very-high-speed integration circuit (VHSIC) hardware description language (VHDL) show that the proposed architecture reduces the hardware complexity by a factor of two, compared with the architecture designed directly from the equalization algorithms. © 1998 IEEE.-
dc.languageEnglish-
dc.titleHardware Architectures of Adaptive Equalizers for the HDTV Receiver-
dc.typeArticle-
dc.relation.issue2-
dc.relation.volume46-
dc.relation.indexSCI-
dc.relation.indexSCIE-
dc.relation.indexSCOPUS-
dc.relation.startpage391-
dc.relation.lastpage404-
dc.relation.journaltitleIEEE Transactions on Signal Processing-
dc.identifier.doi10.1109/78.655424-
dc.identifier.scopusid2-s2.0-0031997005-
dc.author.googleChae S.S.-
dc.author.googlePan S.B.-
dc.author.googleLee Hun G.-
dc.author.googlePark R.-H.-
dc.author.googleLee Byung-Uk-
dc.contributor.scopusid이병욱(56124513700)-
dc.date.modifydate20211116100820-
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엘텍공과대학 > 전자공학과 > Journal papers
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