ELECTRONICS LETTERS vol. 38, no. 13, pp. 626 - 627
IEE-INST ELEC ENG
SCI; SCIE; SCOPUS
A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results shock that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage and temperature variations.