Packet Processing Schemes Using Tree for Internet Routers

Abstract

Rapid growth of internet traffic requires more internet bandwidth and high-speed packet processing in internet routers. IP address lookup in routers is an essential operation that should be performed in real-time for routers where hundreds of million packets arrive per second. Routers also need to perform packet classification in order to support the demand of multimedia data and service requirement and to provide different quality of services according to packet flow. Unlike traditional routers, which forward packets based on destination address only, routers with packet classification capability can forward packets based on multiple header fields. Performing classification quickly on an arbitrary number of fields is known to be very difficult and has poor worst-case performance. The most important performance metric in address lookup or packet classification is the number of memory accesses since it is directly related to the processing time. Through performing in-depth researches on tree architecture, this dissertation proposes three new efficient architectures for IP address lookup and a new architecture for packet classification. Performance evaluation results show that for storing about 40000 routing entries, the proposed ‘2-way BPT’ requires a single 301.7 KByte SRAM and an address lookup is achieved by 11 memory accesses in average. The proposed ‘Multiway BPT’ requires a single 280 KByte SRAM and an address lookup is achieved by 5.9 memory accesses in average. The proposed ‘EnBiT’ which is a hardware-based architecture requires a 1600-entry TCAM and total 325.7 kbyte SRAM and an address lookup is achieved by one memory access. As the proposed packet classification architecture, ‘DPT_PC’ requires very small number of memory accesses and small memory size compared to previous works. It also shows very good characteristics in scalability toward large classifier.