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High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling

Title
High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling
Authors
Choi, InjunKim, Ji-Hoon
Ewha Authors
김지훈
Issue Date
2017
Journal Title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN
1549-8328JCR Link

1558-0806JCR Link
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS vol. 64, no. 7, pp. 1937 - 1948
Keywords
NB-LDPC codesoverlap schedulelow latency check node processingmemory reuse technique
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Indexed
SCI; SCIE; SCOPUS WOS
Document Type
Article
Abstract
Non-binary LDPC (NB-LDPC) codes offer better error correcting performance than their binary counterparts. However, to achieve excellent performance, decoding complexity and large memory are required, which makes it difficult to implement the high-throughput decoder. This paper presents a fully overlapped NB-LDPC decoder using three proposed techniques to improve throughput performance. First, an early bubble check is presented to reduce the initialization latency of the check node processing (CNP). Second, the CNP and variable node processing (VNP) are overlapped with the proposed backward memory scan method to hide the CNP latency within the VNP. Finally, we propose a redundant memory reuse technique to further decrease the latency of a single decoding iteration. We implemented the high-throughput decoder for (160, 80) regular (2, 4) NB-LDPC code over GF (64). The iteration latency was decreased by up to 57.5% with our three proposed methods. The proposed decoder achieved a throughput of 2.22 Gb/s at a 625-MHz frequency with 2.96-M gates in a 65-nm CMOS process. The proposed decoder showed outstanding area efficiency compared with the state-of-the-art decoders.
DOI
10.1109/TCSI.2017.2677518
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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