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High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling
- High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling
- Choi, Injun; Kim, Ji-Hoon
- Ewha Authors
- Issue Date
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS vol. 64, no. 7, pp. 1937 - 1948
- NB-LDPC codes; overlap schedule; low latency check node processing; memory reuse technique
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- SCI; SCIE; SCOPUS
- Document Type
- Non-binary LDPC (NB-LDPC) codes offer better error correcting performance than their binary counterparts. However, to achieve excellent performance, decoding complexity and large memory are required, which makes it difficult to implement the high-throughput decoder. This paper presents a fully overlapped NB-LDPC decoder using three proposed techniques to improve throughput performance. First, an early bubble check is presented to reduce the initialization latency of the check node processing (CNP). Second, the CNP and variable node processing (VNP) are overlapped with the proposed backward memory scan method to hide the CNP latency within the VNP. Finally, we propose a redundant memory reuse technique to further decrease the latency of a single decoding iteration. We implemented the high-throughput decoder for (160, 80) regular (2, 4) NB-LDPC code over GF (64). The iteration latency was decreased by up to 57.5% with our three proposed methods. The proposed decoder achieved a throughput of 2.22 Gb/s at a 625-MHz frequency with 2.96-M gates in a 65-nm CMOS process. The proposed decoder showed outstanding area efficiency compared with the state-of-the-art decoders.
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