Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 반효경 | * |
dc.date.accessioned | 2018-12-03T16:30:10Z | - |
dc.date.available | 2018-12-03T16:30:10Z | - |
dc.date.issued | 2018 | * |
dc.identifier.isbn | 9781538636497 | * |
dc.identifier.other | OAK-23901 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/247173 | - |
dc.description.abstract | In this paper, we present a storage performance accelerator that utilizes a small size of fast NVRAM along with HDD. To do so, we first characterize the storage access patterns for different application types, and make two prominent observations that can be exploited in managing NVRAM storage efficiently. The first observation is that a bulk of storage I/O does not happen on a single specific partition, but it is varied significantly for different application categories. Our second observation is that there are more than 40% of single access data in storage I/Os due to the existence of host-side buffer cache. Based on these observations, we show that acceleration of storage performance can be maximized by using NVRAM as a back-end storage partition (such as file system, journal area, or swap area) rather than using it as a cache device. Specifically, we propose an architecture that uses NVRAM as a swap, a journal, and a file system partitions, respectively, for graph visualization, database, and multimedia streaming applications. Empirical evaluation results show that our storage architecture with application-aware NVRAM allocation reduces the total I/O time by 24% on average and up to 52% compared to the case that uses NVRAM as a cache device. © 2018 IEEE. | * |
dc.description.sponsorship | National Research Foundation of Korea | * |
dc.language | English | * |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | * |
dc.subject | hybrid storage | * |
dc.subject | I/O | * |
dc.subject | NVRAM | * |
dc.subject | storage cache | * |
dc.subject | storage system | * |
dc.title | Accelerating Storage Performance with NVRAM by Considering Application's I/O Characteristics | * |
dc.type | Conference Paper | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 383 | * |
dc.relation.lastpage | 389 | * |
dc.relation.journaltitle | Proceedings - 2018 IEEE International Conference on Big Data and Smart Computing, BigComp 2018 | * |
dc.identifier.doi | 10.1109/BigComp.2018.00063 | * |
dc.identifier.scopusid | 2-s2.0-85048470342 | * |
dc.author.google | Kim J. | * |
dc.author.google | Bahn H. | * |
dc.contributor.scopusid | 반효경(7003994561) | * |
dc.date.modifydate | 20240315133816 | * |