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dc.contributor.author박성민-
dc.date.accessioned2018-06-02T08:13:49Z-
dc.date.available2018-06-02T08:13:49Z-
dc.date.issued2004-
dc.identifier.issn0271-4310-
dc.identifier.otherOAK-17941-
dc.identifier.urihttp://dspace.ewha.ac.kr/handle/2015.oak/243888-
dc.description.abstractA 5-Gb/s clock and data recovery (CDR) circuit, incorporating 625MHz interpolating voltage-controlled oscillators (VCO) and four-phase 1/8-rate phase detectors (PD), is demonstrated. The PD provides linear characteristic that is proportional to the phase difference between the four-phase clocks and the input 5-Gb/s data, and hence produces four-demultiplexed 1.25-Gb/s outputs. The VCO is designed as a four-stage differential ring oscillator, employing the half-rate clock technique so that it can provide 1/8-rate clocks with delay interpolation. Test chips are fabricated in a 0.25μm CMOS technology. The whole chip occupies the area of 1.7×1.4mm2 together with on-chip low pass filters, i.e. two 16pF capacitors and 63kΩ resistors. Post-layout simulations show that the recovered data output exhibits 40ps p-p jitter characteristic for 223 - 1 PRBS serial NRZ input. Chip core dissipates 130mW from a single 2.5V supply.-
dc.description.sponsorshipInstitute of Electrical and Electronics Engineers, IEEE;IEEE Cirquits and Systems Society-
dc.languageEnglish-
dc.titleA 5-Gb/s 1/8-rate CMOS clock and data recovery circuit-
dc.typeConference Paper-
dc.relation.volume4-
dc.relation.indexSCOPUS-
dc.relation.startpageIV-
dc.relation.lastpage293-IV-296-
dc.relation.journaltitleProceedings - IEEE International Symposium on Circuits and Systems-
dc.identifier.scopusid2-s2.0-4344609520-
dc.author.googleKwon J.K.-
dc.author.googleHeo T.K.-
dc.author.googleCho S.-B.-
dc.author.googlePark S.M.-
dc.contributor.scopusid박성민(7501832231)-
dc.date.modifydate20180601095639-
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엘텍공과대학 > 전자공학과 > Journal papers
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