View : 170 Download: 0

A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit

Title
A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit
Authors
Kwon J.K.Heo T.K.Cho S.-B.Park S.M.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2004
Journal Title
Proceedings - IEEE International Symposium on Circuits and Systems
ISSN
0271-4310JCR Link
Citation
Proceedings - IEEE International Symposium on Circuits and Systems vol. 4, pp. IV - 293-IV-296
Indexed
SCOPUS scopus
Document Type
Conference Paper
Abstract
A 5-Gb/s clock and data recovery (CDR) circuit, incorporating 625MHz interpolating voltage-controlled oscillators (VCO) and four-phase 1/8-rate phase detectors (PD), is demonstrated. The PD provides linear characteristic that is proportional to the phase difference between the four-phase clocks and the input 5-Gb/s data, and hence produces four-demultiplexed 1.25-Gb/s outputs. The VCO is designed as a four-stage differential ring oscillator, employing the half-rate clock technique so that it can provide 1/8-rate clocks with delay interpolation. Test chips are fabricated in a 0.25μm CMOS technology. The whole chip occupies the area of 1.7×1.4mm2 together with on-chip low pass filters, i.e. two 16pF capacitors and 63kΩ resistors. Post-layout simulations show that the recovered data output exhibits 40ps p-p jitter characteristic for 223 - 1 PRBS serial NRZ input. Chip core dissipates 130mW from a single 2.5V supply.
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE