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A 1.5 Gbps transceiver chipset in 0.13-μm CMOS for serial digital interface

Title
A 1.5 Gbps transceiver chipset in 0.13-μm CMOS for serial digital interface
Authors
Lee K.Kim S.-H.Park S.M.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2017
Journal Title
Journal of Semiconductor Technology and Science
ISSN
1598-1657JCR Link
Citation
vol. 17, no. 4, pp. 552 - 560
Keywords
CMOSDigital interfaceEqualizationPre-emphasisReceiverSerial linksTransmitter
Publisher
Institute of Electronics Engineers of Korea
Indexed
SCIE; SCOPUS; KCI WOS scopus
Abstract
This paper presents a transceiver chipset realized in a 0.13-mm CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of 1.485 mm2, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of 1.44 mm2. © 2017, Institute of Electronics Engineers of Korea. All rights reserved.
DOI
10.5573/JSTS.2017.17.4.552
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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