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dc.contributor.author신형순*
dc.contributor.author선우경*
dc.date.accessioned2016-08-29T12:08:45Z-
dc.date.available2016-08-29T12:08:45Z-
dc.date.issued2016*
dc.identifier.issn0268-1242*
dc.identifier.issn1361-6641*
dc.identifier.otherOAK-19121*
dc.identifier.urihttps://dspace.ewha.ac.kr/handle/2015.oak/231799-
dc.description.abstractThis paper proposes a new bias scheme for a crossbar array that can improve the power consumption and read margin. The concept of the newly proposed 5/12 bias scheme is to reduce the bias of the unselected cells for power consumption and the bias of half-selected cells for a reduced line voltage drop of the selected cell. In the 5/12 bias scheme, the unselected word line and bit line are biased to 5 x V-app/12 and 7 x V-app/12, respectively. The electrical characteristics of the 5/12 bias scheme are evaluated by HSPICE simulations and it is found that appropriate nonlinearity of selector can simultaneously achieve low power consumption and high read margin for 5/12 bias scheme.*
dc.languageEnglish*
dc.publisherIOP PUBLISHING LTD*
dc.subjectnonvolatile memory*
dc.subjectcrossbar array*
dc.subjectReRAM*
dc.subjectpower consumption*
dc.subjectread margin*
dc.titleA new bias scheme for a low power consumption ReRAM crossbar array*
dc.typeArticle*
dc.relation.issue8*
dc.relation.volume31*
dc.relation.indexSCIE*
dc.relation.indexSCOPUS*
dc.relation.journaltitleSEMICONDUCTOR SCIENCE AND TECHNOLOGY*
dc.identifier.doi10.1088/0268-1242/31/8/085009*
dc.identifier.wosidWOS:000380223200017*
dc.identifier.scopusid2-s2.0-84979590536*
dc.author.googleSun, Wookyung*
dc.author.googleChoi, Sujin*
dc.author.googleShin, Hyungsoon*
dc.contributor.scopusid신형순(7404012125)*
dc.contributor.scopusid선우경(7404011223)*
dc.date.modifydate20240322125227*
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공과대학 > 전자전기공학전공 > Journal papers
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