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A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS
- A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS
- Lee K.; Hong C.; Ying H.; Kim D.; Kim S.H.; Park S.M.
- Ewha Authors
- SCOPUS Author ID
- Issue Date
- Journal Title
- ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
- ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), pp. 235 - 236
- CMOS; frequency synthesizer; PLL; ring VCO; tuning range
- Institute of Electrical and Electronics Engineers Inc.
- Document Type
- Conference Paper
- This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2. © 2015 IEEE.
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- 엘텍공과대학 > 전자공학과 > Journal papers
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