Evaluations of hardware and software-based context switching methods in cortex-M3 for embedded applications

Abstract

In contrast to the previous ARM microprocessor, the ARM Cortex-M3 processor provides a method for accelerating context switching, which is supported by dedicated hardware logic vis a software interrupt (or trap). In general, it is expected that retaining the context of a task using hardware will reduce the context switching time, but it is also known that software interrupts or traps incur their own overheads. In this study, we propose an algorithm for analyzing the performance of context switching methods in uC/OS-II the Cortex-M3. According to our experimental analysis, we obtained the same results using the algorithm in an ideal state and in a real application. We expect that the algorithms and experimental results described in this study may help embedded system designers by providing quantitative measures in the context switching time of Cortex-M3 using a real-world application. © 2015 SERSC.