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DABC-NV: A buffer cache architecture for mobile systems with heterogeneous flash memories

Title
DABC-NV: A buffer cache architecture for mobile systems with heterogeneous flash memories
Authors
Park J.Lee E.Bahn H.
Ewha Authors
반효경
SCOPUS Author ID
반효경scopus
Issue Date
2012
Journal Title
IEEE Transactions on Consumer Electronics
ISSN
0098-3063JCR Link
Citation
vol. 58, no. 4, pp. 1237 - 1245
Indexed
SCI; SCIE; SCOPUS WOS scopus
Abstract
Flash memory is widely used in mobile consumer electronics devices due to its good properties such as small size, shock resistance, and low-power consumption. However, the cost of flash memory is still high to accommodate ever-growing mobile applications and multimedia contents. Using MLC (multilevel cell) technologies is an efficient solution to extend the storage capacity, but it degrades the performance of flash memory significantly compared to the original storage based on SLC (single-level cell) technologies. To bridge the characteristics of the two technologies, this paper presents a new buffer cache management scheme that uses both MLC and SLC together and considers their heterogeneous characteristics. By allocating cache space based on the characteristics of each storage media as well as I/O operation types and reference history of buffered blocks, the proposed scheme improves the I/O performance of mobile systems by 24% on average and up to 180% compared to the CLOCK algorithm. Moreover, it guarantees high reliability of file data by adopting recently emerging non-volatile RAMs in a certain portion of the buffer cache. © 2011 IEEE.
DOI
10.1109/TCE.2012.6414991
Appears in Collections:
엘텍공과대학 > 컴퓨터공학과 > Journal papers
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