Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성민 | * |
dc.date.accessioned | 2016-08-28T11:08:40Z | - |
dc.date.available | 2016-08-28T11:08:40Z | - |
dc.date.issued | 2007 | * |
dc.identifier.isbn | 1424408539 | * |
dc.identifier.isbn | 9781424408535 | * |
dc.identifier.issn | 0193-6530 | * |
dc.identifier.other | OAK-12983 | * |
dc.identifier.uri | https://dspace.ewha.ac.kr/handle/2015.oak/229035 | - |
dc.description.abstract | A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 2S1-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2. ©2007 IEEE. | * |
dc.language | English | * |
dc.title | A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation | * |
dc.type | Conference Paper | * |
dc.relation.index | SCOPUS | * |
dc.relation.startpage | 56 | * |
dc.relation.lastpage | 57+41 | * |
dc.relation.journaltitle | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | * |
dc.identifier.doi | 10.1109/ISSCC.2007.373585 | * |
dc.identifier.scopusid | 2-s2.0-34548849100 | * |
dc.author.google | Yoo K. | * |
dc.author.google | Lee D. | * |
dc.author.google | Han G. | * |
dc.author.google | Park S.M. | * |
dc.author.google | Oh W.S. | * |
dc.contributor.scopusid | 박성민(7501832231) | * |
dc.date.modifydate | 20240322125443 | * |