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A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation

Title
A 1.2V 5.2mW 40dB 2.5Gb/s limiting amplifier in 0.18μm CMOS using negative-impedance compensation
Authors
Yoo K.Lee D.Han G.Park S.M.Oh W.S.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2007
Journal Title
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN
0193-6530JCR Link
Citation
pp. 56 - 57+41
Indexed
SCOPUS scopus
Abstract
A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 2S1-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2. ©2007 IEEE.
DOI
10.1109/ISSCC.2007.373585
ISBN
1424408539; 9781424408535
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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