DSpace at EWHA: A hybrid PRAM and STT-RAM cache architecture for extending the lifetime of PRAM caches

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DC Field	Value	Language
dc.contributor.author	박상수	*
dc.contributor.author	주용수	*
dc.date.accessioned	2016-08-28T11:08:25Z	-
dc.date.available	2016-08-28T11:08:25Z	-
dc.date.issued	2013	*
dc.identifier.issn	1556-6056	*
dc.identifier.other	OAK-10853	*
dc.identifier.uri	https://dspace.ewha.ac.kr/handle/2015.oak/227369	-
dc.description.abstract	Cache memories; Design Styles; Hardware; Memory Structures; Redundant design; Reliability; Testing and Fault-Tolerance	*
dc.language	English	*
dc.title	A hybrid PRAM and STT-RAM cache architecture for extending the lifetime of PRAM caches	*
dc.type	Article	*
dc.relation.issue	2	*
dc.relation.volume	12	*
dc.relation.index	SCIE	*
dc.relation.index	SCOPUS	*
dc.relation.startpage	55	*
dc.relation.lastpage	58	*
dc.relation.journaltitle	IEEE Computer Architecture Letters	*
dc.identifier.doi	10.1109/L-CA.2012.24	*
dc.identifier.wosid	WOS:000328935900005	*
dc.identifier.scopusid	2-s2.0-84891142395	*
dc.author.google	Joo Y.	*
dc.author.google	Park S.	*
dc.contributor.scopusid	박상수(39762312300)	*
dc.contributor.scopusid	주용수(7102315422)	*
dc.date.modifydate	20240322133703	*