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dc.contributor.author박상수-
dc.contributor.author주용수-
dc.date.accessioned2016-08-28T11:08:25Z-
dc.date.available2016-08-28T11:08:25Z-
dc.date.issued2013-
dc.identifier.issn1556-6056-
dc.identifier.otherOAK-10853-
dc.identifier.urihttp://dspace.ewha.ac.kr/handle/2015.oak/227369-
dc.description.abstractCache memories; Design Styles; Hardware; Memory Structures; Redundant design; Reliability; Testing and Fault-Tolerance-
dc.languageEnglish-
dc.titleA hybrid PRAM and STT-RAM cache architecture for extending the lifetime of PRAM caches-
dc.typeArticle-
dc.relation.issue2-
dc.relation.volume12-
dc.relation.indexSCIE-
dc.relation.indexSCOPUS-
dc.relation.startpage55-
dc.relation.lastpage58-
dc.relation.journaltitleIEEE Computer Architecture Letters-
dc.identifier.doi10.1109/L-CA.2012.24-
dc.identifier.wosidWOS:000328935900005-
dc.identifier.scopusid2-s2.0-84891142395-
dc.author.googleJoo Y.-
dc.author.googlePark S.-
dc.contributor.scopusid박상수(39762312300)-
dc.contributor.scopusid주용수(7102315422)-
dc.date.modifydate20180104081001-
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엘텍공과대학 > 컴퓨터공학과 > Journal papers
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