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A low-power gigabit CMOS limiting amplifier using negative impedance compensation and its application

Title
A low-power gigabit CMOS limiting amplifier using negative impedance compensation and its application
Authors
Han J.Yoo K.Lee D.Park K.Oh W.Park S.M.
Ewha Authors
박성민
SCOPUS Author ID
박성민scopus
Issue Date
2012
Journal Title
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN
1063-8210JCR Link
Citation
vol. 20, no. 3, pp. 393 - 399
Indexed
SCIE; SCOPUS WOS scopus
Abstract
This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 2 31-1 pseudorandom bit sequence inputs, 9.5-mV pp input sensitivity for 10 - 12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm 2. The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10 -12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm 2. © 2011 IEEE.
DOI
10.1109/TVLSI.2010.2104333
Appears in Collections:
엘텍공과대학 > 전자공학과 > Journal papers
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