View : 37 Download: 0
A low-power gigabit CMOS limiting amplifier using negative impedance compensation and its application
- A low-power gigabit CMOS limiting amplifier using negative impedance compensation and its application
- Han J.; Yoo K.; Lee D.; Park K.; Oh W.; Park S.M.
- Ewha Authors
- SCOPUS Author ID
- Issue Date
- Journal Title
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- vol. 20, no. 3, pp. 393 - 399
- SCIE; SCOPUS
- This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18-μ m CMOS process, demonstrating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for 2 31-1 pseudorandom bit sequence inputs, 9.5-mV pp input sensitivity for 10 - 12 bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 × 0.1 mm 2. The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18-μm CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB Ω transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, -16-dBm optical sensitivity for 10 -12 BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 × 0.45 mm 2. © 2011 IEEE.
- Appears in Collections:
- 엘텍공과대학 > 전자공학과 > Journal papers
- Files in This Item:
There are no files associated with this item.
- RIS (EndNote)
- XLS (Excel)
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.