For the simulation of the architecture for a magnetoresistive random access memory (MRAM) based on GMR (giant magnetoresistance) and a MTJ (magnetic tunnel junction) cell having a hysteretic characteristics, a macro model showing this hysteresis is required. Also, a new sense amplifier is needed for the MRAM because the cell is destroyed at high voltages. Thus, this work presents a macro model and a sensing circuit for a MRAM. The macro model is realized by using a six-terminal subcircuit, which emulates the hysteretic nature of MRAM cell, and read/write simulations are possible. A current-source bit-line-clamped sense amplifier maintains a low voltage on the bit line during the full VDD sensing, so it is suitable for sensing the MRAM cell.