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Packet Forwarding Architectures for High Performance Internet Routers

Title
Packet Forwarding Architectures for High Performance Internet Routers
Authors
정여진
Issue Date
2004
Department/Major
과학기술대학원 정보통신학과
Publisher
이화여자대학교 대학원
Degree
Master
Abstract
Address lookup is one of the main functions of the Internet routers and a very important feature in evaluating router performance. As the Internet traffic keeps growing and the number of routing table entries is continuously growing, efficient address-lookup mechanisms are essential. In recent years, various fast address-lookup schemes have been proposed, but most of those schemes are not practical in terms of the memory size required for routing table and the complexity required in table update. Modern internet routers are required to classify flows of incoming packets in order to support the variety of quality of service levels, and it is achieved through packet classification. For a given classifier defining packet attributes or contents, packet classification is the process of identifying the highest priority rule to which a packet conforms. In other words, packet classification is the process of classifying incoming packets into “class” in an internet router. Since packet classification should be performed in real-time based on the thousands of pre-defined multi-field rules, it is a challenging operation. The notable characteristic of real classifiers is that a packet matches only a small number of distinct source-destination prefix pairs. Therefore, a lot of schemes have been proposed to filter rules based on source and destination prefix fields. However, most of the previous schemes have problems caused by inefficient searches and huge memory size required. In this dissertation, we proposed three efficient schemes, one for IP address lookup and two for packet classification. The proposed scheme for IP address lookup is a parallel IP address lookup architecture based on multiple hashing. The proposed scheme shows very good performance in required memory size, the number of memory accesses, and table update. We have evaluated the performance of the proposed scheme through simulation using data from MAE-WEST router. The simulation result shows that the proposed scheme requires a single memory access for the address lookup of each route when 222kbytes of memory and a few-hundred-entry TCAM are used for about 30,000 entry routing table. The first proposed scheme for packet classification is based on parallel multiple hashing in source-destination prefix tuples and linked-list search in remaining fields for rules with the same source and destination prefixes. Prefix grouping is also proposed to reduce the number of tuples. Simulation results using real databases show that the proposed scheme requires very small number of memory accesses and O(N) memory space for N rule classifier. It also shows very good characteristics in rule updating and scalability toward large classifier. Finally, we proposed a memory-efficient two-dimensional search scheme using source and destination prefix pairs. By constructing codeword binary prefix tree, source prefix search and destination prefix search are simultaneously performed in one binary prefix tree. Moreover, the proposed two-dimensional binary prefix tree does not include any empty internal nodes, and therefore, memory waste of previous trie-based structures is completely eliminated.
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